{
  "schema_version": "1.6.1",
  "id": "RPI-CVE-2026-53374",
  "modified": "2026-10-09T11:39:44Z",
  "upstream": [
    "CVE-2026-53374"
  ],
  "published": "2026-07-19T10:00:50Z",
  "summary": "drm/amdgpu: zero-initialize GART table on allocation",
  "details": "In the Linux kernel, the following vulnerability has been resolved:\n\ndrm/amdgpu: zero-initialize GART table on allocation\n\nGART TLB is flushed after unmapping but not after mapping. Since\namdgpu_bo_create_kernel() does not zero-initialize the buffer, when a\nsingle PTE is written the TLB may speculatively load other uninitialized\nentries from the same cacheline. Those garbage entries can appear valid,\nand a subsequent write to another PTE in the same cacheline may cause the\nGPU to use a stale garbage PTE from the TLB.\n\nFix this by calling memset_io() to zero-initialize the GART table with\ngart_pte_flags immediately after allocation.\n\nUsing AMDGPU_GEM_CREATE_VRAM_CLEARED, SDMA-based clear will not work\nsince SDMA needs GART to be initialized to work.\n\n(cherry picked from commit d9af8263b82b6eaa60c5718e0c6631c5037e4b24)",
  "severity": [
    {
      "type": "CVSS_V3",
      "score": "CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:C/C:H/I:H/A:H"
    }
  ],
  "affected": [
    {
      "package": {
        "ecosystem": "Raspberry Pi OS:12",
        "name": "linux"
      },
      "versions": [
        "1:6.1.47-1+rpt4"
      ],
      "ecosystem_specific": {
        "binaries": [
          {
            "binary_name": "linux-image-6.1.0-rpi3-rpi-2712",
            "binary_version": "1:6.1.47-1+rpt4"
          },
          {
            "binary_name": "linux-image-6.1.0-rpi3-rpi-v6",
            "binary_version": "1:6.1.47-1+rpt4"
          },
          {
            "binary_name": "linux-image-6.1.0-rpi3-rpi-v7",
            "binary_version": "1:6.1.47-1+rpt4"
          },
          {
            "binary_name": "linux-image-6.1.0-rpi3-rpi-v7l",
            "binary_version": "1:6.1.47-1+rpt4"
          },
          {
            "binary_name": "linux-image-6.1.0-rpi3-rpi-v8",
            "binary_version": "1:6.1.47-1+rpt4"
          }
        ]
      },
      "database_specific": {
        "per_version": {
          "1:6.1.47-1+rpt4": {
            "linux_commit": "655fc658a15ae7a6f37103754adb39ba52a9a14e",
            "upstream_version": "6.1.47",
            "assessment": "commit ancestry (strak rule)",
            "upstream_fixed": "6.1.175",
            "compiled_filter": false
          }
        }
      }
    }
  ],
  "references": [
    {
      "type": "ADVISORY",
      "url": "https://www.cve.org/CVERecord?id=CVE-2026-53374"
    },
    {
      "type": "FIX",
      "url": "https://git.kernel.org/stable/c/40df11255d71b02e20e70579f1b12b687e396e26"
    },
    {
      "type": "FIX",
      "url": "https://git.kernel.org/stable/c/91fbb5e635c8fb1b49e15c19da06480089ef719f"
    },
    {
      "type": "FIX",
      "url": "https://git.kernel.org/stable/c/8ae8b9e74bab94aab1d79f1688129bcc61c8b29a"
    },
    {
      "type": "FIX",
      "url": "https://git.kernel.org/stable/c/b17175d0a375b3ed5e81597dac4983fdb46e478d"
    },
    {
      "type": "FIX",
      "url": "https://git.kernel.org/stable/c/791941be5da125d9a1b228582bfdc300c05d05b3"
    },
    {
      "type": "FIX",
      "url": "https://git.kernel.org/stable/c/e6c2e6c2e1fa066968a16aca1cb66cd1bdde7741"
    }
  ],
  "database_specific": {
    "source": "https://git.kernel.org/pub/scm/linux/security/vulns.git",
    "upstream_modified": "2026-08-05T13:16:28Z",
    "severity": {
      "source": "kernel CNA",
      "cvss_v3_score": 8.8,
      "cvss_v3_severity": "High",
      "scenario": "AV:L - The bug is reached when a local process with access to /dev/dri/renderD* issues AMDGPU DRM ioctls (GEM_CREATE, CS) that bind GTT buffers through amdgpu_ttm_backend_bind() \u2192 amdgpu_gart_bind(), writing GART PTEs without a TLB flush. This is a local GPU driver ioctl path, not a network protocol.\nAC:L - An attacker with render-node access can reliably trigger GART PTE writes by allocating and binding GTT-domain buffers via standard ioctls; they control mapping timing and concurrency. Uninitialized VRAM contents at driver init are not an attacker-uncontrollable gate for triggering the stale-TLB condition.\nPR:L - All AMDGPU GEM/CS ioctls require DRM_AUTH|DRM_RENDER_ALLOW, which is satisfied by membership in the render/video group on typical desktop, workstation, and cloud-GPU instances\u2014not real root in the init namespace.\nUI:N - Exploitation requires only programmatic ioctl and GPU command submission; no victim interaction such as opening files or mounting filesystems is needed beyond the attacker already having render-node access.\nS:C - Stale garbage GART PTEs in the GPU TLB can cause the GPU to DMA to/from arbitrary physical pages outside the driver's intended mappings, bypassing the GART/IOMMU address-translation boundary that is supposed to confine GPU memory access.\nC:H - Speculatively loaded garbage PTEs that appear valid can redirect GPU reads to unintended physical memory, including kernel and other processes' pages, constituting arbitrary memory disclosure via rogue DMA.\nI:H - Those same stale valid PTEs can redirect GPU writes to arbitrary physical addresses, enabling arbitrary memory corruption and potential code execution through DMA write primitives.\nA:H - GPU DMA through invalid or garbage PTEs to unintended physical addresses can cause IOMMU faults, machine checks, GPU hangs, or kernel oops/panic, producing full system availability loss."
    }
  }
}